A Highly Reliable SEU Hardened Shift Register

Low Power Dissipation SEU-hardened CMOS Latch

This paper reports three design improvements for CMOS latches hardened against single event upset (SEU) based on three memory cells appeared in recent years. The improvement drastically reduces static power dissipation, reduces the number of transistors required in the VLSI, especially when they are used in the Gate Array. The original cells and the new improved latches are compared. It is show...

Circuit Designs for Low-power and Seu- Hardened Systems Circuit Designs for Low-power and Seu- Hardened Systems Vii Circuit Designs for Low-power and Seu-hardened Systems

OF THESIS Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science Electrical Engineering The University of New Mexico Albuquerque, New Mexico

A microdroplet-based shift register.

A microfluidic device is presented for the serial formation, storage and retrieval of water microdroplets in oil. The principle of operation is similar to that of an electronic shift register. Droplets, considered as units of information, can be arrayed and serially shifted within the device, allowing the controllable positioning of the emulsions and the creation of interfaces between drops. Us...

Low cost and highly reliable radiation hardened latch design in 65 nm

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when pa...